Advances in semiconductor processing and device design have resulted in computing devices being incorporated in a seemingly endless variety of tools and machines, ranging from conventional programmable computers to communication equipment and entertainment devices. Irrespective of its end purpose, a computing device typically includes a central processing unit (CPU), random access memory (RAM), and an addressing and communication mechanism enabling data exchange between the CPU and the RAM. In a computing device, data is stored, communicated and manipulated in the form of signals (e.g., voltage, current, optical and the like). The CPU contains circuitry for logically manipulating the signals, whereas the memory contains circuitry for storing the signals before, during and after the CPU's manipulation of those signals.
Conventional CPUs, memory devices and data communication mechanisms are mass produced as solid-state electronic devices. Although sometimes referred to as “semiconductor devices”, solid-state electronic devices rely on the electrical behavior of multiple types of solid materials, including metals, semiconductors, and insulators. The techniques and equipment for producing solid-state devices have improved dramatically over time to enable the production of devices such as switches, capacitors, resistors, and interconnections with sub-micron scale features.
Today, memory devices implement hundreds of megabits of storage in a single integrated circuit. These devices include volatile memory (e.g., dynamic random access memory (DRAM) and static random access memory (SRAM)), non-volatile memory (e.g., electrically erasable programmable read only memory (EEPROM), flash EPROM, ferroelectric DRAM), and the like. Memory manufacturing systems and processes continue to push the limits of fine-geometry patterning and fabrication technology.
Performance of the memory components of a computing device is becoming an increasingly important determinant of overall system performance. Larger quantities of memory enable a greater variety of applications and functions to be implemented by the computing device and may reduce or eliminate the need for separate mass storage devices. Higher speed memory supports higher CPU processing frequencies, making the computing devices more useful for complex or real-time tasks. Denser memory devices support a growing variety of battery-powered electronic devices, such as laptop computers, PDAs, multifunction cellular telephones, and the like. At the same time, many of these applications benefit from reduced power consumption.
In many cases, improvements in semiconductor processing technology have led to the manufacture of denser, larger, faster and more power efficient memory devices. In many cases, the solid-state electronic behavior of the devices improves as the devices become smaller. Unfortunately, conventional memory, such as silicon-based DRAM memory, has reached a point where continued reduction in the size of conventional semiconductor memory cells is expected to adversely affect at least some of these important parameters and add undesirably to costs.
One reason for the reduced speed and increased power consumption at smaller dimensions is that memory cells usually implement a capacitor for each stored bit of information. A capacitor is a charge storage device formed by conductive plates that are separated by an insulator. As capacitors become smaller the quantity of charge that can be stored is reduced. To serve as a reliable storage device in a memory cell, a capacitor needs sufficient capacity to hold a signal at a level that can be reliably detected as data. Moreover, conventional capacitors lose their stored charge over time through the switch or transistor that is attached to each memory location. Transistors are inherently “leaky” devices and some of the charge stored in a capacitor dissipates or leaks over time. Memory cells based on smaller capacitors are more sensitive to leakage problems because they simply have less charge that can be lost before the stored data becomes irretrievable. They are also subject to reduced reliability.
To overcome the transient nature of capacitive storage, memory devices use refresh circuitry that frequently reads out a stored signal, amplifies it to a higher level, and stores it back into the capacitor. As the physical area allotted to the capacitor is decreased, it becomes increasingly difficult to maintain the same charge storage capacity in the smaller available area. Unless the leakages can be reduced in conjunction with the reduced storage capacity, the rate at which the capacitor must be refreshed increases. In turn, higher capacitor refresh rates reduce the percentage of time that a memory cell is available for reading and writing data. Moreover, a greater percentage of the total power consumption of the memory device is then used to refresh the memory. Even when the device is in a dormant or inactive state, traditional DRAM requires continuous refreshing and therefore continuous power consumption. Accordingly, researchers are actively seeking new ways of storing data signals that overcome the problems associated with smaller lithographic features and complex capacitor geometries in conventional capacitor-based memory cells.
Memory cell designers have attempted to maintain low refresh rates in smaller memory cells by boosting the amount of capacitance that can be formed in a given amount of chip area. Boosting capacitance often involves increasing the surface area of the capacitor's charge holding material, which is very difficult to do when the overall size of the capacitor is shrinking. While designers have had some success at controlling surface area by forming the charge holding material into three-dimensional trench and stacked capacitor designs, it is unlikely that these techniques alone can be relied on to create sufficient capacitances in smaller cells. The solid-state electronic behaviors upon which cell performance is predicated begin to break down as the dimensions of various cell features become smaller such that a capacitor can no longer store sufficient charge for sufficient time to be useful in a memory cell.
One potential way to mitigate these problems is via molecular devices that implement some or all components of an electronic device or system with molecular scale structures and components. These molecular scale structures and components exhibit molecular rather than solid-state behavior, which can provide enhanced performance in many instances. Moreover, because molecules retain their essential properties down to the individual molecule level, molecular-scale components and device structures can be scaled (or shrunk) as future processing tools and technologies are developed.
Widespread use of molecules in electronic devices (e.g., switches, capacitors, conductors, and the like) depends on the development of attachment chemistries and processes that achieve high yield at reasonable throughputs and costs. To date, however, equipment vendors and tool development engineers have not developed efficient tools and processes for applying attachment chemistries that can be used in molecular electronic device manufacture. For widespread use, molecular scale components require repeatable processes that are able to attach desired chemical species to substrates, other device structures, and each other. In addition, robust processes for forming molecular structures are needed to enable new types of components (e.g., micron or sub-micron size electrochemical cells for charge storage) to be implemented in conjunction with semiconductor components.
It is desirable for molecular device manufacturing techniques to be compatible with existing semiconductor industry processes and to use existing semiconductor industry tools or improvements thereof. However, molecular device processing is sensitive to many variables and conditions that do not have the same impact on semiconductor processing. For example, water is present throughout most semiconductor manufacturing processes as a cleaning fluid and in the form of ambient humidity. Water, however, can have destructive effects on some molecular processes because water molecules interfere with the attachment chemistry or destroy the active molecules. Similarly, thin native oxide layers and ultra-low contaminant levels are tolerable in semiconductor processes because the bulk effects of these aberrant features are minimal in comparison to the overall device function. In contrast, when devices are manufactured with molecular-scale features, these molecular-scale defects can become significant.
Another problem faces memory designers trying to increase information density (e.g., the amount of information that can be stored in a given area of a chip containing memory). With the practical constraints of current DRAM technology, each memory cell with a conventional solid-state capacitor can only store one bit of information. Accordingly, it would be desirable to have a memory (and processing systems and methods therefor) with improved information storage density, e.g., by using a memory cell that can reliably store more than two discrete states.
In view of the above, there is a need for improved memory devices. In particular, there is a need for molecular memory cells, molecular memory arrays, and electronic devices including molecular memory. In addition, there is a need for more efficient tools and processes for manufacturing molecular memories. Further, there is a need for molecular memory that can be manufactured using techniques that are compatible with existing semiconductor manufacturing practices so that semiconductor devices and interconnections can be manufactured monolithically with molecular memory.